Chapter 10

In the ATmega32 what memory area is assigned to the interrupt vector table?

True or false. The TIMSK register is not a bit-addressable register.

True or false. For each of Timer0 and Timer 1, there is a unique address in the interrupt vector table.

True or false. An address location is assigned to each of the external hardware interrupts INT0, INT1, and INT2.

Assume that the INT0 bit for external hardware interrupt is enabled and is negative edge-triggered. When is the interrupt activated? How does this intermpt work when it is activated.

Explain the role of INTF0 and INT0 in the execution of external interrupt 0 .

Explain the difference between low-level and falling edge-triggered interrupts.

True or false. INT0-INT2 must be configured as an input pin for a hardware interrupt to come in.

Explain what happens if an interrupt is activated while the AVR is serving an interrupt.